diff -Naur linux-2.4.36.2.orig/drivers/char/drm/drm_drv.h linux-2.4.36.2/driver s/char/drm/drm_drv.h --- linux-2.4.36.2.orig/drivers/char/drm/drm_drv.h 2008-05-21 03:25:33.000 000000 +0200 +++ linux-2.4.36.2/drivers/char/drm/drm_drv.h 2008-05-21 03:26:24.000000000 + 0200 @@ -496,7 +496,7 @@ #endif if ( dev->lock.hw_lock ) { dev->sigdata.lock = dev->lock.hw_lock = NULL; /* SHM removed */ - dev->lock.pid = 0; + dev->lock.filp = 0; wake_up_interruptible( &dev->lock.lock_queue ); } up( &dev->struct_sem ); @@ -770,7 +770,7 @@ if ( dev->lock.hw_lock && _DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock) && - dev->lock.pid == current->pid ) { + dev->lock.filp == filp ) { DRM_DEBUG( "Process %d dead, freeing lock for context %d\n", current->pid, _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock) ); @@ -799,7 +799,7 @@ } if ( DRM(lock_take)( &dev->lock.hw_lock->lock, DRM_KERNEL_CONTEXT ) ) { - dev->lock.pid = priv->pid; + dev->lock.filp = filp; dev->lock.lock_time = jiffies; atomic_inc( &dev->counts[_DRM_STAT_LOCKS] ); break; /* Got lock */ @@ -969,7 +969,7 @@ } if ( DRM(lock_take)( &dev->lock.hw_lock->lock, lock.context ) ) { - dev->lock.pid = current->pid; + dev->lock.filp = filp; dev->lock.lock_time = jiffies; atomic_inc( &dev->counts[_DRM_STAT_LOCKS] ); break; /* Got lock */ diff -Naur linux-2.4.36.2.orig/drivers/char/drm/drm_lock.h linux-2.4.36.2/drive rs/char/drm/drm_lock.h --- linux-2.4.36.2.orig/drivers/char/drm/drm_lock.h 2008-05-21 03:25:34.000 000000 +0200 +++ linux-2.4.36.2/drivers/char/drm/drm_lock.h 2008-05-21 03:26:24.000000000 + 0200 @@ -78,7 +78,7 @@ { unsigned int old, new, prev; - dev->lock.pid = 0; + dev->lock.filp = 0; do { old = *lock; new = context | _DRM_LOCK_HELD; @@ -91,19 +91,19 @@ __volatile__ unsigned int *lock, unsigned int context) { unsigned int old, new, prev; - pid_t pid = dev->lock.pid; + struct file *filp = dev->lock.filp; - dev->lock.pid = 0; + dev->lock.filp = 0; do { old = *lock; new = 0; prev = cmpxchg(lock, old, new); } while (prev != old); if (_DRM_LOCK_IS_HELD(old) && _DRM_LOCKING_CONTEXT(old) != context) { - DRM_ERROR("%d freed heavyweight lock held by %d (pid %d)\n", + DRM_ERROR("%d freed heavyweight lock held by %d (%p)\n", context, _DRM_LOCKING_CONTEXT(old), - pid); + filp); return 1; } wake_up_interruptible(&dev->lock.lock_queue); diff -Naur linux-2.4.36.2.orig/drivers/char/drm/drm_os_linux.h linux-2.4.36.2/d rivers/char/drm/drm_os_linux.h --- linux-2.4.36.2.orig/drivers/char/drm/drm_os_linux.h 2008-05-21 03:25:34.000 000000 +0200 +++ linux-2.4.36.2/drivers/char/drm/drm_os_linux.h 2008-05-21 03:26:24.000 000000 +0200 @@ -3,6 +3,20 @@ #include /* For task queue support */ #include +#define DRMFILE struct file * +#define DRM_IOCTL_ARGS struct inode *inode, struct file *filp, unsigned int cmd, unsigned long data +#define DRM_ERR(d) -(d) +#define DRM_CURRENTPID current->pid +#define DRM_UDELAY(d) udelay(d) +#define DRM_READ8(map, offset) readb(((unsigned long)(map)->handle) + (offset)) +#define DRM_READ32(map, offset) readl(((unsigned long)(map)->ha ndle) + (offset)) +#define DRM_WRITE8(map, offset, val) writeb(val, ((unsigned long)(map)->hand le) + (offset)) +#define DRM_WRITE32(map, offset, val) writel(val, ((unsigned long)(map)->hand le) + (offset)) +#define DRM_MEMORYBARRIER() mb() +#define DRM_DEVICE drm_file_t *priv = filp->private_data; \ + drm_device_t *dev = priv->dev + +#define DRM_IRQ_ARGS int irq, void *arg, struct pt_regs *regs /* For data going from/to the kernel through the ioctl argument */ #define DRM_COPY_FROM_USER_IOCTL(arg1, arg2, arg3) \ @@ -11,6 +25,28 @@ #define DRM_COPY_TO_USER_IOCTL(arg1, arg2, arg3) \ if ( copy_to_user(arg1, &arg2, arg3) ) \ return -EFAULT +/* Other copying of data from/to kernel space */ +#define DRM_COPY_FROM_USER(arg1, arg2, arg3) \ + copy_from_user(arg1, arg2, arg3) +#define DRM_COPY_TO_USER(arg1, arg2, arg3) \ + copy_to_user(arg1, arg2, arg3) +/* Macros for copyfrom user, but checking readability only once */ +#define DRM_VERIFYAREA_READ( uaddr, size ) \ + verify_area( VERIFY_READ, uaddr, size ) +#define DRM_COPY_FROM_USER_UNCHECKED(arg1, arg2, arg3) \ + __copy_from_user(arg1, arg2, arg3) +#define DRM_GET_USER_UNCHECKED(val, uaddr) \ + __get_user(val, uaddr) + + +/* malloc/free without the overhead of DRM(alloc) */ +#define DRM_MALLOC(x) kmalloc(x, GFP_KERNEL) +#define DRM_FREE(x,size) kfree(x) + +#define DRM_HZ HZ + +#define DRM_WAKEUP( queue ) wake_up_interruptible( queue ) +#define DRM_INIT_WAITQUEUE( queue ) init_waitqueue_head( queue ) #define DRM_GETSAREA() \ diff -Naur linux-2.4.36.2.orig/drivers/char/drm/drmP.h linux-2.4.36.2/drivers/c har/drm/drmP.h --- linux-2.4.36.2.orig/drivers/char/drm/drmP.h 2008-05-21 03:25:34.000000000 + 0200 +++ linux-2.4.36.2/drivers/char/drm/drmP.h 2008-05-21 03:26:24.000000000 + 0200 @@ -336,6 +336,16 @@ (_map) = (_dev)->context_sareas[_ctx]; \ } while(0) +#define LOCK_TEST_WITH_RETURN( dev, filp ) \ +do { \ + if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || \ + dev->lock.filp != filp ) { \ + DRM_ERROR( "%s called without lock held\n", \ + __FUNCTION__ ); \ + return -EINVAL; \ + } \ +} while(0) + typedef int drm_ioctl_t( struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg ); @@ -502,7 +512,11 @@ typedef struct drm_lock_data { drm_hw_lock_t *hw_lock; /* Hardware lock */ +#if 0 pid_t pid; /* PID of lock holder (0=kernel) */ +#else + struct file *filp; +#endif wait_queue_head_t lock_queue; /* Queue of blocked processes */ unsigned long lock_time; /* Time of last lock in jiffies */ } drm_lock_data_t; @@ -585,6 +599,8 @@ drm_map_t *map; } drm_map_list_t; +typedef drm_map_t drm_local_map_t; + #if __HAVE_VBL_IRQ typedef struct drm_vbl_sig { diff -Naur linux-2.4.36.2.orig/drivers/char/drm/mga_dma.c linux-2.4.36.2/driver s/char/drm/mga_dma.c --- linux-2.4.36.2.orig/drivers/char/drm/mga_dma.c 2008-05-21 03:25:34.000 000000 +0200 +++ linux-2.4.36.2/drivers/char/drm/mga_dma.c 2008-05-21 03:26:24.000000000 + 0200 @@ -693,7 +693,7 @@ drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; drm_lock_t lock; - LOCK_TEST_WITH_RETURN( dev ); + LOCK_TEST_WITH_RETURN( dev, filp ); if ( copy_from_user( &lock, (drm_lock_t *)arg, sizeof(lock) ) ) return -EFAULT; @@ -731,7 +731,7 @@ drm_device_t *dev = priv->dev; drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; - LOCK_TEST_WITH_RETURN( dev ); + LOCK_TEST_WITH_RETURN( dev, filp ); return mga_do_dma_reset( dev_priv ); } @@ -774,7 +774,7 @@ drm_dma_t d; int ret = 0; - LOCK_TEST_WITH_RETURN( dev ); + LOCK_TEST_WITH_RETURN( dev, filp ); if ( copy_from_user( &d, (drm_dma_t *)arg, sizeof(d) ) ) return -EFAULT; diff -Naur linux-2.4.36.2.orig/drivers/char/drm/mga_drv.h linux-2.4.36.2/driver s/char/drm/mga_drv.h --- linux-2.4.36.2.orig/drivers/char/drm/mga_drv.h 2008-05-21 03:25:34.000 000000 +0200 +++ linux-2.4.36.2/drivers/char/drm/mga_drv.h 2008-05-21 03:26:24.000000000 + 0200 @@ -193,16 +193,6 @@ } \ } while (0) -#define LOCK_TEST_WITH_RETURN( dev ) \ -do { \ - if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || \ - dev->lock.pid != current->pid ) { \ - DRM_ERROR( "%s called without lock held\n", \ - __FUNCTION__ ); \ - return -EINVAL; \ - } \ -} while (0) - #define WRAP_TEST_WITH_RETURN( dev_priv ) \ do { \ if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \ diff -Naur linux-2.4.36.2.orig/drivers/char/drm/mga_state.c linux-2.4.36.2/driv ers/char/drm/mga_state.c --- linux-2.4.36.2.orig/drivers/char/drm/mga_state.c 2008-05-21 03:25:34.000 000000 +0200 +++ linux-2.4.36.2/drivers/char/drm/mga_state.c 2008-05-21 03:26:24.000000000 + 0200 @@ -881,7 +881,7 @@ drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_clear_t clear; - LOCK_TEST_WITH_RETURN( dev ); + LOCK_TEST_WITH_RETURN( dev, filp ); if ( copy_from_user( &clear, (drm_mga_clear_t *) arg, sizeof(clear) ) ) return -EFAULT; @@ -908,7 +908,7 @@ drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - LOCK_TEST_WITH_RETURN( dev ); + LOCK_TEST_WITH_RETURN( dev, filp ); if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS ) sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; @@ -935,7 +935,7 @@ drm_mga_buf_priv_t *buf_priv; drm_mga_vertex_t vertex; - LOCK_TEST_WITH_RETURN( dev ); + LOCK_TEST_WITH_RETURN( dev, filp ); if ( copy_from_user( &vertex, (drm_mga_vertex_t *)arg, @@ -977,7 +977,7 @@ drm_mga_buf_priv_t *buf_priv; drm_mga_indices_t indices; - LOCK_TEST_WITH_RETURN( dev ); + LOCK_TEST_WITH_RETURN( dev, filp ); if ( copy_from_user( &indices, (drm_mga_indices_t *)arg, @@ -1020,7 +1020,7 @@ drm_mga_iload_t iload; DRM_DEBUG( "%s:\n", __FUNCTION__ ); - LOCK_TEST_WITH_RETURN( dev ); + LOCK_TEST_WITH_RETURN( dev, filp ); if ( copy_from_user( &iload, (drm_mga_iload_t *)arg, sizeof(iload) ) ) return -EFAULT; @@ -1063,7 +1063,7 @@ drm_mga_blit_t blit; DRM_DEBUG( "%s\n", __FUNCTION__ ); - LOCK_TEST_WITH_RETURN( dev ); + LOCK_TEST_WITH_RETURN( dev, filp ); if ( copy_from_user( &blit, (drm_mga_blit_t *)arg, sizeof(blit) ) ) return -EFAULT; diff -Naur linux-2.4.36.2.orig/drivers/char/drm/radeon_cp.c linux-2.4.36.2/driv ers/char/drm/radeon_cp.c --- linux-2.4.36.2.orig/drivers/char/drm/radeon_cp.c 2008-05-21 03:25:34.000 000000 +0200 +++ linux-2.4.36.2/drivers/char/drm/radeon_cp.c 2008-05-21 03:26:24.000000000 + 0200 @@ -33,14 +33,10 @@ #include "drm.h" #include "radeon_drm.h" #include "radeon_drv.h" -#include "drm_os_linux.h" -#include /* For task queue support */ -#include #define RADEON_FIFO_DEBUG 0 - /* CP microcode (from ATI) */ static u32 R200_cp_microcode[][2] = { { 0x21007000, 0000000000 }, @@ -614,14 +610,14 @@ & RADEON_RB2D_DC_BUSY) ) { return 0; } - udelay( 1 ); + DRM_UDELAY( 1 ); } #if RADEON_FIFO_DEBUG DRM_ERROR( "failed!\n" ); radeon_status( dev_priv ); #endif - return -EBUSY; + return DRM_ERR(EBUSY); } static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv, @@ -635,14 +631,14 @@ int slots = ( RADEON_READ( RADEON_RBBM_STATUS ) & RADEON_RBBM_FIFOCNT_MASK ); if ( slots >= entries ) return 0; - udelay( 1 ); + DRM_UDELAY( 1 ); } #if RADEON_FIFO_DEBUG DRM_ERROR( "failed!\n" ); radeon_status( dev_priv ); #endif - return -EBUSY; + return DRM_ERR(EBUSY); } static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv ) @@ -660,14 +656,14 @@ radeon_do_pixcache_flush( dev_priv ); return 0; } - udelay( 1 ); + DRM_UDELAY( 1 ); } #if RADEON_FIFO_DEBUG DRM_ERROR( "failed!\n" ); radeon_status( dev_priv ); #endif - return -EBUSY; + return DRM_ERR(EBUSY); } @@ -775,7 +771,7 @@ cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR ); RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr ); - *dev_priv->ring.head = cur_read_ptr; + SET_RING_HEAD( dev_priv, cur_read_ptr ); dev_priv->ring.tail = cur_read_ptr; } @@ -883,18 +879,22 @@ /* Set the write pointer delay */ RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 ); - RADEON_READ( RADEON_CP_RB_WPTR_DELAY ); /* read back to propagate */ /* Initialize the ring buffer's read and write pointers */ cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR ); RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr ); - *dev_priv->ring.head = cur_read_ptr; + SET_RING_HEAD( dev_priv, cur_read_ptr ); dev_priv->ring.tail = cur_read_ptr; +#if __REALLY_HAVE_AGP if ( !dev_priv->is_pci ) { RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR, - dev_priv->ring_rptr->offset ); - } else { + dev_priv->ring_rptr->offset + - dev->agp->base + + dev_priv->agp_vm_start); + } else +#endif + { drm_sg_mem_t *entry = dev->sg; unsigned long tmp_ofs, page_ofs; @@ -903,8 +903,8 @@ RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]); - DRM_DEBUG( "ring rptr: offset=0x%08x handle=0x%08lx\n", - entry->busaddr[page_ofs], + DRM_DEBUG( "ring rptr: offset=0x%08lx handle=0x%08lx\n", + (unsigned long) entry->busaddr[page_ofs], entry->handle + tmp_ofs ); } @@ -919,19 +919,19 @@ + RADEON_SCRATCH_REG_OFFSET ); dev_priv->scratch = ((__volatile__ u32 *) - dev_priv->ring.head + + dev_priv->ring_rptr->handle + (RADEON_SCRATCH_REG_OFFSET / sizeof(u32))); RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 ); /* Writeback doesn't seem to work everywhere, test it first */ - writel(0, &dev_priv->scratch[1]); + DRM_WRITE32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0 ); RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef ); for ( tmp = 0 ; tmp < dev_priv->usec_timeout ; tmp++ ) { - if ( readl( &dev_priv->scratch[1] ) == 0xdeadbeef ) + if ( DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1) ) == 0xdeadbeef ) break; - udelay(1); + DRM_UDELAY( 1 ); } if ( tmp < dev_priv->usec_timeout ) { @@ -983,7 +983,7 @@ dev_priv = DRM(alloc)( sizeof(drm_radeon_private_t), DRM_MEM_DRIVER ); if ( dev_priv == NULL ) - return -ENOMEM; + return DRM_ERR(ENOMEM); memset( dev_priv, 0, sizeof(drm_radeon_private_t) ); @@ -993,7 +993,7 @@ DRM_ERROR( "PCI GART memory not allocated!\n" ); dev->dev_private = (void *)dev_priv; radeon_do_cleanup_cp(dev); - return -EINVAL; + return DRM_ERR(EINVAL); } dev_priv->usec_timeout = init->usec_timeout; @@ -1002,7 +1002,7 @@ DRM_DEBUG( "TIMEOUT problem!\n" ); dev->dev_private = (void *)dev_priv; radeon_do_cleanup_cp(dev); - return -EINVAL; + return DRM_ERR(EINVAL); } dev_priv->is_r200 = (init->func == RADEON_INIT_R200_CP); @@ -1018,7 +1018,7 @@ DRM_DEBUG( "BAD cp_mode (%x)!\n", init->cp_mode ); dev->dev_private = (void *)dev_priv; radeon_do_cleanup_cp(dev); - return -EINVAL; + return DRM_ERR(EINVAL); } switch ( init->fb_bpp ) { @@ -1085,12 +1085,19 @@ RADEON_ROUND_PREC_8TH_PIX); DRM_GETSAREA(); + + dev_priv->fb_offset = init->fb_offset; + dev_priv->mmio_offset = init->mmio_offset; + dev_priv->ring_offset = init->ring_offset; + dev_priv->ring_rptr_offset = init->ring_rptr_offset; + dev_priv->buffers_offset = init->buffers_offset; + dev_priv->agp_textures_offset = init->agp_textures_offset; if(!dev_priv->sarea) { DRM_ERROR("could not find sarea!\n"); dev->dev_private = (void *)dev_priv; radeon_do_cleanup_cp(dev); - return -EINVAL; + return DRM_ERR(EINVAL); } DRM_FIND_MAP( dev_priv->fb, init->fb_offset ); @@ -1098,35 +1105,35 @@ DRM_ERROR("could not find framebuffer!\n"); dev->dev_private = (void *)dev_priv; radeon_do_cleanup_cp(dev); - return -EINVAL; + return DRM_ERR(EINVAL); } DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset ); if(!dev_priv->mmio) { DRM_ERROR("could not find mmio region!\n"); dev->dev_private = (void *)dev_priv; radeon_do_cleanup_cp(dev); - return -EINVAL; + return DRM_ERR(EINVAL); } DRM_FIND_MAP( dev_priv->cp_ring, init->ring_offset ); if(!dev_priv->cp_ring) { DRM_ERROR("could not find cp ring region!\n"); dev->dev_private = (void *)dev_priv; radeon_do_cleanup_cp(dev); - return -EINVAL; + return DRM_ERR(EINVAL); } DRM_FIND_MAP( dev_priv->ring_rptr, init->ring_rptr_offset ); if(!dev_priv->ring_rptr) { DRM_ERROR("could not find ring read pointer!\n"); dev->dev_private = (void *)dev_priv; radeon_do_cleanup_cp(dev); - return -EINVAL; + return DRM_ERR(EINVAL); } DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset ); if(!dev_priv->buffers) { DRM_ERROR("could not find dma buffer region!\n"); dev->dev_private = (void *)dev_priv; radeon_do_cleanup_cp(dev); - return -EINVAL; + return DRM_ERR(EINVAL); } if ( !dev_priv->is_pci ) { @@ -1136,7 +1143,7 @@ DRM_ERROR("could not find agp texture region!\n"); dev->dev_private = (void *)dev_priv; radeon_do_cleanup_cp(dev); - return -EINVAL; + return DRM_ERR(EINVAL); } } @@ -1144,6 +1151,7 @@ (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle + init->sarea_priv_offset); +#if __REALLY_HAVE_AGP if ( !dev_priv->is_pci ) { DRM_IOREMAP( dev_priv->cp_ring, dev ); DRM_IOREMAP( dev_priv->ring_rptr, dev ); @@ -1154,9 +1162,11 @@ DRM_ERROR("could not find ioremap agp regions!\n"); dev->dev_private = (void *)dev_priv; radeon_do_cleanup_cp(dev); - return -EINVAL; + return DRM_ERR(EINVAL); } - } else { + } else +#endif + { dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset; dev_priv->ring_rptr->handle = @@ -1192,9 +1202,6 @@ DRM_DEBUG( "dev_priv->agp_buffers_offset 0x%lx\n", dev_priv->agp_buffers_offset ); - dev_priv->ring.head = ((__volatile__ u32 *) - dev_priv->ring_rptr->handle); - dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle; dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle + init->ring_size / sizeof(u32)); @@ -1206,14 +1213,13 @@ dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; -#if __REALLY_HAVE_SG if ( dev_priv->is_pci ) { if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart, &dev_priv->bus_pci_gart)) { DRM_ERROR( "failed to init PCI GART!\n" ); dev->dev_private = (void *)dev_priv; radeon_do_cleanup_cp(dev); - return -ENOMEM; + return DRM_ERR(ENOMEM); } /* Turn on PCI GART */ @@ -1236,15 +1242,12 @@ RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */ RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */ } else { -#endif /* __REALLY_HAVE_SG */ /* Turn off PCI GART */ tmp = RADEON_READ( RADEON_AIC_CNTL ) & ~RADEON_PCIGART_TRANSLATE_EN; RADEON_WRITE( RADEON_AIC_CNTL, tmp ); -#if __REALLY_HAVE_SG } -#endif /* __REALLY_HAVE_SG */ radeon_cp_load_microcode( dev_priv ); radeon_cp_init_ring_buffer( dev, dev_priv ); @@ -1262,20 +1265,32 @@ { DRM_DEBUG( "\n" ); +#if _HAVE_DMA_IRQ + /* Make sure interrupts are disabled here because the uninstall ioctl + * may not have been called from userspace and after dev_private + * is freed, it's too late. + */ + if ( dev->irq ) DRM(irq_uninstall)(dev); +#endif + if ( dev->dev_private ) { drm_radeon_private_t *dev_priv = dev->dev_private; +#if __REALLY_HAVE_AGP if ( !dev_priv->is_pci ) { - DRM_IOREMAPFREE( dev_priv->cp_ring, dev ); - DRM_IOREMAPFREE( dev_priv->ring_rptr, dev ); - DRM_IOREMAPFREE( dev_priv->buffers, dev ); - } else { -#if __REALLY_HAVE_SG + if ( dev_priv->cp_ring != NULL ) + DRM_IOREMAPFREE( dev_priv->cp_ring, dev ); + if ( dev_priv->ring_rptr != NULL ) + DRM_IOREMAPFREE( dev_priv->ring_rptr, dev ); + if ( dev_priv->buffers != NULL ) + DRM_IOREMAPFREE( dev_priv->buffers, dev ); + } else +#endif + { if (!DRM(ati_pcigart_cleanup)( dev, dev_priv->phys_pci_gart, dev_priv->bus_pci_gart )) DRM_ERROR( "failed to cleanup PCI GART!\n" ); -#endif /* __REALLY_HAVE_SG */ } DRM(free)( dev->dev_private, sizeof(drm_radeon_private_t), @@ -1286,15 +1301,184 @@ return 0; } -int radeon_cp_init( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +/* This code will reinit the Radeon CP hardware after a resume from disc. + * AFAIK, it would be very difficult to pickle the state at suspend time, so + * here we make sure that all Radeon hardware initialisation is re-done withou t + * affecting running applications. This function is called radeon_do_resume_c p() + * as it was derived from radeon_init_cp, where most of the initialisation tak es + * place during DRI init. + * + * This patch is NOT to be confused with my and Michel Daenzer's earlier DRI + * reinit work, which de- and re-initialised the complete DRI at every VT + * switch. + * + * Charl P. Botha + */ +static int radeon_do_resume_cp( drm_device_t *dev) +{ + drm_radeon_private_t *dev_priv; + u32 tmp; + DRM_DEBUG( "\n" ); + + DRM_DEBUG("Starting radeon_do_resume_cp()\n"); + + /* get the existing dev_private */ + dev_priv = dev->dev_private; + +#if !defined(PCIGART_ENABLED) + /* PCI support is not 100% working, so we disable it here. + */ + if ( dev_priv->is_pci ) { + DRM_ERROR( "PCI GART not yet supported for Radeon!\n" ); + radeon_do_cleanup_cp(dev); + return DRM_ERR(EINVAL); + } +#endif + + if ( dev_priv->is_pci && !dev->sg ) { + DRM_ERROR( "PCI GART memory not allocated!\n" ); + radeon_do_cleanup_cp(dev); + return DRM_ERR(EINVAL); + } + + if ( dev_priv->usec_timeout < 1 || + dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) { + DRM_DEBUG( "TIMEOUT problem!\n" ); + radeon_do_cleanup_cp(dev); + return DRM_ERR(EINVAL); + } + + if ( ( dev_priv->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) && + ( dev_priv->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) { + DRM_DEBUG( "BAD cp_mode (%x)!\n", dev_priv->cp_mode ); + radeon_do_cleanup_cp(dev); + return DRM_ERR(EINVAL); + } + + if(!dev_priv->sarea) { + DRM_ERROR("could not find sarea!\n"); + radeon_do_cleanup_cp(dev); + return DRM_ERR(EINVAL); + } + + if(!dev_priv->fb) { + DRM_ERROR("could not find framebuffer!\n"); + radeon_do_cleanup_cp(dev); + return DRM_ERR(EINVAL); + } + + if(!dev_priv->mmio) { + DRM_ERROR("could not find mmio region!\n"); + radeon_do_cleanup_cp(dev); + return DRM_ERR(EINVAL); + } + + if(!dev_priv->cp_ring) { + DRM_ERROR("could not find cp ring region!\n"); + radeon_do_cleanup_cp(dev); + return DRM_ERR(EINVAL); + } + + if(!dev_priv->ring_rptr) { + DRM_ERROR("could not find ring read pointer!\n"); + radeon_do_cleanup_cp(dev); + return DRM_ERR(EINVAL); + } + + if(!dev_priv->buffers) { + DRM_ERROR("could not find dma buffer region!\n"); + radeon_do_cleanup_cp(dev); + return DRM_ERR(EINVAL); + } + + if ( !dev_priv->is_pci ) { + if(!dev_priv->agp_textures) { + DRM_ERROR("could not find agp texture region!\n"); + radeon_do_cleanup_cp(dev); + return DRM_ERR(EINVAL); + } + } + + if ( !dev_priv->is_pci ) { + if(!dev_priv->cp_ring->handle || + !dev_priv->ring_rptr->handle || + !dev_priv->buffers->handle) { + DRM_ERROR("could not find ioremap agp regions!\n"); + radeon_do_cleanup_cp(dev); + return DRM_ERR(EINVAL); + } + } else { + DRM_DEBUG( "dev_priv->cp_ring->handle %p\n", + dev_priv->cp_ring->handle ); + DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n", + dev_priv->ring_rptr->handle ); + DRM_DEBUG( "dev_priv->buffers->handle %p\n", + dev_priv->buffers->handle ); + } + + + DRM_DEBUG( "dev_priv->agp_size %d\n", + dev_priv->agp_size ); + DRM_DEBUG( "dev_priv->agp_vm_start 0x%x\n", + dev_priv->agp_vm_start ); + DRM_DEBUG( "dev_priv->agp_buffers_offset 0x%lx\n", + dev_priv->agp_buffers_offset ); + +#if __REALLY_HAVE_AGP + if ( !dev_priv->is_pci ) { + /* Turn off PCI GART + */ + tmp = RADEON_READ( RADEON_AIC_CNTL ) + & ~RADEON_PCIGART_TRANSLATE_EN; + RADEON_WRITE( RADEON_AIC_CNTL, tmp ); + } else +#endif + { + /* I'm not so sure about this ati_picgart_init after at resume- time... */ + if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart, + &dev_priv->bus_pci_gart)) { + DRM_ERROR( "failed to init PCI GART!\n" ); + radeon_do_cleanup_cp(dev); + return DRM_ERR(ENOMEM); + } + + tmp = RADEON_READ( RADEON_AIC_CNTL ) + | RADEON_PCIGART_TRANSLATE_EN; + RADEON_WRITE( RADEON_AIC_CNTL, tmp ); + + /* set PCI GART page-table base address + */ + RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart ); + + /* set address range for PCI address translate + */ + RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->agp_vm_start ); + RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->agp_vm_start + + dev_priv->agp_size - 1); + + /* Turn off AGP aperture -- is this required for PCIGART? + */ + RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */ + RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */ + } + + radeon_cp_load_microcode( dev_priv ); + radeon_cp_init_ring_buffer( dev, dev_priv ); + + radeon_do_engine_reset( dev ); + + return 0; +} + + +int radeon_cp_init( DRM_IOCTL_ARGS ) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + DRM_DEVICE; drm_radeon_init_t init; - if ( copy_from_user( &init, (drm_radeon_init_t *)arg, sizeof(init) ) ) - return -EFAULT; + LOCK_TEST_WITH_RETURN( dev, filp ); + + DRM_COPY_FROM_USER_IOCTL( init, (drm_radeon_init_t *)data, sizeof(init) ); switch ( init.func ) { case RADEON_INIT_CP: @@ -1304,18 +1488,16 @@ return radeon_do_cleanup_cp( dev ); } - return -EINVAL; + return DRM_ERR(EINVAL); } -int radeon_cp_start( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int radeon_cp_start( DRM_IOCTL_ARGS ) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "%s\n", __FUNCTION__ ); + DRM_DEBUG( "\n" ); - LOCK_TEST_WITH_RETURN( dev ); + LOCK_TEST_WITH_RETURN( dev, filp ); if ( dev_priv->cp_running ) { DRM_DEBUG( "%s while CP running\n", __FUNCTION__ ); @@ -1335,20 +1517,20 @@ /* Stop the CP. The engine must have been idled before calling this * routine. */ -int radeon_cp_stop( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int radeon_cp_stop( DRM_IOCTL_ARGS ) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_cp_stop_t stop; int ret; - DRM_DEBUG( "%s\n", __FUNCTION__ ); + DRM_DEBUG( "\n" ); - LOCK_TEST_WITH_RETURN( dev ); + LOCK_TEST_WITH_RETURN( dev, filp ); - if ( copy_from_user( &stop, (drm_radeon_init_t *)arg, sizeof(stop) ) ) - return -EFAULT; + DRM_COPY_FROM_USER_IOCTL( stop, (drm_radeon_cp_stop_t *)data, sizeof(st op) ); + + if (!dev_priv->cp_running) + return 0; /* Flush any pending CP commands. This ensures any outstanding * commands are exectuted by the engine before we turn it off. @@ -1377,21 +1559,52 @@ return 0; } + +void radeon_do_release( drm_device_t *dev ) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + int ret; + + if (dev_priv) { + if (dev_priv->cp_running) { + /* Stop the cp */ + while ((ret = radeon_do_cp_idle( dev_priv )) != 0) { + DRM_DEBUG("radeon_do_cp_idle %d\n", ret); +#ifdef __linux__ + schedule(); +#else + tsleep(&ret, PZERO, "rdnrel", 1); +#endif + } + radeon_do_cp_stop( dev_priv ); + radeon_do_engine_reset( dev ); + } + + /* Disable *all* interrupts */ + RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 ); + + /* Free memory heap structures */ + radeon_mem_takedown( &(dev_priv->agp_heap) ); + radeon_mem_takedown( &(dev_priv->fb_heap) ); + + /* deallocate kernel resources */ + radeon_do_cleanup_cp( dev ); + } +} + /* Just reset the CP ring. Called as part of an X Server engine reset. */ -int radeon_cp_reset( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int radeon_cp_reset( DRM_IOCTL_ARGS ) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "%s\n", __FUNCTION__ ); + DRM_DEBUG( "\n" ); - LOCK_TEST_WITH_RETURN( dev ); + LOCK_TEST_WITH_RETURN( dev, filp ); if ( !dev_priv ) { DRM_DEBUG( "%s called before init done\n", __FUNCTION__ ); - return -EINVAL; + return DRM_ERR(EINVAL); } radeon_do_cp_reset( dev_priv ); @@ -1402,27 +1615,33 @@ return 0; } -int radeon_cp_idle( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int radeon_cp_idle( DRM_IOCTL_ARGS ) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "%s\n", __FUNCTION__ ); + DRM_DEBUG( "\n" ); - LOCK_TEST_WITH_RETURN( dev ); + LOCK_TEST_WITH_RETURN( dev, filp ); return radeon_do_cp_idle( dev_priv ); } -int radeon_engine_reset( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +/* Added by Charl P. Botha to call radeon_do_resume_cp(). + */ +int radeon_cp_resume( DRM_IOCTL_ARGS ) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; - DRM_DEBUG( "%s\n", __FUNCTION__ ); + DRM_DEVICE; + + return radeon_do_resume_cp(dev); +} - LOCK_TEST_WITH_RETURN( dev ); + +int radeon_engine_reset( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + DRM_DEBUG( "\n" ); + + LOCK_TEST_WITH_RETURN( dev, filp ); return radeon_do_engine_reset( dev ); } @@ -1434,7 +1653,7 @@ /* KW: Deprecated to say the least: */ -int radeon_fullscreen(struct inode *inode, struct file *filp, unsigned int cmd , unsigned long data) +int radeon_fullscreen( DRM_IOCTL_ARGS ) { return 0; } @@ -1491,7 +1710,7 @@ } if (t) { - udelay(1); + DRM_UDELAY( 1 ); dev_priv->stats.freelist_loops++; } } @@ -1508,7 +1727,7 @@ drm_buf_t *buf; int i, t; int start; - u32 done_age = readl(&dev_priv->scratch[1]); + u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)); if ( ++dev_priv->last_buf >= dma->buf_count ) dev_priv->last_buf = 0; @@ -1520,7 +1739,7 @@ for ( i = start ; i < dma->buf_count ; i++ ) { buf = dma->buflist[i]; buf_priv = buf->dev_private; - if ( buf->pid == 0 || (buf->pending && + if ( buf->filp == 0 || (buf->pending && buf_priv->age <= done_age) ) { dev_priv->stats.requested_bufs++; buf->pending = 0; @@ -1557,10 +1776,10 @@ { drm_radeon_ring_buffer_t *ring = &dev_priv->ring; int i; - u32 last_head = GET_RING_HEAD(ring); + u32 last_head = GET_RING_HEAD( dev_priv ); for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - u32 head = GET_RING_HEAD(ring); + u32 head = GET_RING_HEAD( dev_priv ); ring->space = (head - ring->tail) * sizeof(u32); if ( ring->space <= 0 ) @@ -1574,7 +1793,7 @@ i = 0; last_head = head; - udelay( 1 ); + DRM_UDELAY( 1 ); } /* FIXME: This return value is ignored in the BEGIN_RING macro! */ @@ -1582,70 +1801,66 @@ radeon_status( dev_priv ); DRM_ERROR( "failed!\n" ); #endif - return -EBUSY; + return DRM_ERR(EBUSY); } -static int radeon_cp_get_buffers( drm_device_t *dev, drm_dma_t *d ) +static int radeon_cp_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t * d ) { int i; drm_buf_t *buf; for ( i = d->granted_count ; i < d->request_count ; i++ ) { buf = radeon_freelist_get( dev ); - if ( !buf ) return -EAGAIN; + if ( !buf ) return DRM_ERR(EBUSY); /* NOTE: broken client */ buf->pid = current->pid; - if ( copy_to_user( &d->request_indices[i], &buf->idx, + if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx, sizeof(buf->idx) ) ) - return -EFAULT; - if ( copy_to_user( &d->request_sizes[i], &buf->total, + return DRM_ERR(EFAULT); + if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total, sizeof(buf->total) ) ) - return -EFAULT; + return DRM_ERR(EFAULT); d->granted_count++; } return 0; } -int radeon_cp_buffers( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int radeon_cp_buffers( DRM_IOCTL_ARGS ) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + DRM_DEVICE; drm_device_dma_t *dma = dev->dma; int ret = 0; drm_dma_t d; - LOCK_TEST_WITH_RETURN( dev ); + LOCK_TEST_WITH_RETURN( dev, filp ); - if ( copy_from_user( &d, (drm_dma_t *)arg, sizeof(d) ) ) - return -EFAULT; + DRM_COPY_FROM_USER_IOCTL( d, (drm_dma_t *)data, sizeof(d) ); /* Please don't send us buffers. */ if ( d.send_count != 0 ) { DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n", - current->pid, d.send_count ); - return -EINVAL; + DRM_CURRENTPID, d.send_count ); + return DRM_ERR(EINVAL); } /* We'll send you buffers. */ if ( d.request_count < 0 || d.request_count > dma->buf_count ) { DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n", - current->pid, d.request_count, dma->buf_count ); - return -EINVAL; + DRM_CURRENTPID, d.request_count, dma->buf_count ); + return DRM_ERR(EINVAL); } d.granted_count = 0; if ( d.request_count ) { - ret = radeon_cp_get_buffers( dev, &d ); + ret = radeon_cp_get_buffers( filp, dev, &d ); } - if ( copy_to_user( (drm_dma_t *)arg, &d, sizeof(d) ) ) - return -EFAULT; + DRM_COPY_TO_USER_IOCTL( (drm_dma_t *)data, d, sizeof(d) ); return ret; } diff -Naur linux-2.4.36.2.orig/drivers/char/drm/radeon_drm.h linux-2.4.36.2/dri vers/char/drm/radeon_drm.h --- linux-2.4.36.2.orig/drivers/char/drm/radeon_drm.h 2008-05-21 03:25:34.000 000000 +0200 +++ linux-2.4.36.2/drivers/char/drm/radeon_drm.h 2008-05-21 03:26:24.000 000000 +0200 @@ -323,12 +323,6 @@ typedef struct { - unsigned char next, prev; - unsigned char in_use; - int age; -} drm_radeon_tex_region_t; - -typedef struct { /* The channel for communication of state information to the * kernel on firing a vertex buffer with either of the * obsoleted vertex/index ioctls. @@ -350,8 +344,8 @@ unsigned int last_dispatch; unsigned int last_clear; - drm_radeon_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REG IONS+1]; - int tex_age[RADEON_NR_TEX_HEAPS]; + drm_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1] ; + unsigned int tex_age[RADEON_NR_TEX_HEAPS]; int ctx_owner; int pfState; /* number of 3d windows (0,1,2ormore) */ int pfCurrentPage; /* which buffer is being displayed? */ @@ -391,12 +385,14 @@ #define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( 0x55, drm_radeon_mem_init_heap_t) #define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR( 0x56, drm_radeon_irq_emit_t) #define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( 0x57, drm_radeon_irq_wait_t) +/* added by Charl P. Botha - see radeon_cp.c for details */ +#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO(0x58) typedef struct drm_radeon_init { enum { RADEON_INIT_CP = 0x01, RADEON_CLEANUP_CP = 0x02, - RADEON_INIT_R200_CP = 0x03, + RADEON_INIT_R200_CP = 0x03 } func; unsigned long sarea_priv_offset; int is_pci; @@ -532,6 +528,10 @@ #define RADEON_PARAM_LAST_CLEAR 4 #define RADEON_PARAM_IRQ_NR 5 #define RADEON_PARAM_AGP_BASE 6 /* card offset of agp base */ +#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */ +#define RADEON_PARAM_STATUS_HANDLE 8 +#define RADEON_PARAM_SAREA_HANDLE 9 +#define RADEON_PARAM_AGP_TEX_HANDLE 10 typedef struct drm_radeon_getparam { int param; diff -Naur linux-2.4.36.2.orig/drivers/char/drm/radeon_drv.h linux-2.4.36.2/dri vers/char/drm/radeon_drv.h --- linux-2.4.36.2.orig/drivers/char/drm/radeon_drv.h 2008-05-21 03:25:34.000 000000 +0200 +++ linux-2.4.36.2/drivers/char/drm/radeon_drv.h 2008-05-21 03:26:24.000 000000 +0200 @@ -31,8 +31,8 @@ #ifndef __RADEON_DRV_H__ #define __RADEON_DRV_H__ -#define GET_RING_HEAD(ring) readl( (volatile u32 *) (ring)->head ) -#define SET_RING_HEAD(ring,val) writel( (val), (volatile u32 *) (ring)->head ) +#define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_r ptr, 0 ) +#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) ) typedef struct drm_radeon_freelist { unsigned int age; @@ -47,7 +47,6 @@ int size; int size_l2qw; - volatile u32 *head; u32 tail; u32 tail_mask; int space; @@ -67,7 +66,7 @@ struct mem_block *prev; int start; int size; - int pid; /* 0: free, -1: heap, other: real pids */ + DRMFILE filp; /* 0: free, -1: heap, other: real files */ }; typedef struct drm_radeon_private { @@ -125,14 +124,21 @@ u32 depth_pitch_offset; drm_radeon_depth_clear_t depth_clear; - - drm_map_t *sarea; - drm_map_t *fb; - drm_map_t *mmio; - drm_map_t *cp_ring; - drm_map_t *ring_rptr; - drm_map_t *buffers; - drm_map_t *agp_textures; + + unsigned long fb_offset; + unsigned long mmio_offset; + unsigned long ring_offset; + unsigned long ring_rptr_offset; + unsigned long buffers_offset; + unsigned long agp_textures_offset; + + drm_local_map_t *sarea; + drm_local_map_t *fb; + drm_local_map_t *mmio; + drm_local_map_t *cp_ring; + drm_local_map_t *ring_rptr; + drm_local_map_t *buffers; + drm_local_map_t *agp_textures; struct mem_block *agp_heap; struct mem_block *fb_heap; @@ -148,22 +154,15 @@ } drm_radeon_buf_priv_t; /* radeon_cp.c */ -extern int radeon_cp_init( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int radeon_cp_start( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int radeon_cp_stop( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int radeon_cp_reset( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int radeon_cp_idle( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int radeon_engine_reset( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int radeon_fullscreen( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int radeon_cp_buffers( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); +extern int radeon_cp_init( DRM_IOCTL_ARGS ); +extern int radeon_cp_start( DRM_IOCTL_ARGS ); +extern int radeon_cp_stop( DRM_IOCTL_ARGS ); +extern int radeon_cp_reset( DRM_IOCTL_ARGS ); +extern int radeon_cp_idle( DRM_IOCTL_ARGS ); +extern int radeon_cp_resume( DRM_IOCTL_ARGS ); +extern int radeon_engine_reset( DRM_IOCTL_ARGS ); +extern int radeon_fullscreen( DRM_IOCTL_ARGS ); +extern int radeon_cp_buffers( DRM_IOCTL_ARGS ); extern void radeon_freelist_reset( drm_device_t *dev ); extern drm_buf_t *radeon_freelist_get( drm_device_t *dev ); @@ -175,39 +174,33 @@ extern int radeon_do_cleanup_pageflip( drm_device_t *dev ); /* radeon_state.c */ -extern int radeon_cp_clear( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int radeon_cp_swap( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int radeon_cp_vertex( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int radeon_cp_indices( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int radeon_cp_texture( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int radeon_cp_stipple( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int radeon_cp_indirect( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int radeon_cp_vertex2(struct inode *inode, struct file *filp,unsigned i nt cmd, unsigned long arg ); -extern int radeon_cp_cmdbuf(struct inode *inode, struct file *filp,unsigned in t cmd, unsigned long arg ); -extern int radeon_cp_getparam(struct inode *inode, struct file *filp,unsigned int cmd, unsigned long arg ); -extern int radeon_cp_flip(struct inode *inode, struct file *filp,unsigned int cmd, unsigned long arg ); - -extern int radeon_mem_alloc(struct inode *inode, struct file *filp,unsigned in t cmd, unsigned long arg ); -extern int radeon_mem_free(struct inode *inode, struct file *filp,unsigned int cmd, unsigned long arg ); -extern int radeon_mem_init_heap(struct inode *inode, struct file *filp,unsigne d int cmd, unsigned long arg ); +extern int radeon_cp_clear( DRM_IOCTL_ARGS ); +extern int radeon_cp_swap( DRM_IOCTL_ARGS ); +extern int radeon_cp_vertex( DRM_IOCTL_ARGS ); +extern int radeon_cp_indices( DRM_IOCTL_ARGS ); +extern int radeon_cp_texture( DRM_IOCTL_ARGS ); +extern int radeon_cp_stipple( DRM_IOCTL_ARGS ); +extern int radeon_cp_indirect( DRM_IOCTL_ARGS ); +extern int radeon_cp_vertex2( DRM_IOCTL_ARGS ); +extern int radeon_cp_cmdbuf( DRM_IOCTL_ARGS ); +extern int radeon_cp_getparam( DRM_IOCTL_ARGS ); +extern int radeon_cp_flip( DRM_IOCTL_ARGS ); + +extern int radeon_mem_alloc( DRM_IOCTL_ARGS ); +extern int radeon_mem_free( DRM_IOCTL_ARGS ); +extern int radeon_mem_init_heap( DRM_IOCTL_ARGS ); extern void radeon_mem_takedown( struct mem_block **heap ); -extern void radeon_mem_release( struct mem_block *heap ); +extern void radeon_mem_release( DRMFILE filp, struct mem_block *heap ); /* radeon_irq.c */ -extern int radeon_irq_emit(struct inode *inode, struct file *filp,unsigned int cmd, unsigned long arg ); -extern int radeon_irq_wait(struct inode *inode, struct file *filp,unsigned int cmd, unsigned long arg ); +extern int radeon_irq_emit( DRM_IOCTL_ARGS ); +extern int radeon_irq_wait( DRM_IOCTL_ARGS ); extern int radeon_emit_and_wait_irq(drm_device_t *dev); extern int radeon_wait_irq(drm_device_t *dev, int swi_nr); extern int radeon_emit_irq(drm_device_t *dev); +extern void radeon_do_release(drm_device_t *dev); /* Flags for stats.boxes */ @@ -281,8 +274,10 @@ #define RADEON_SCRATCH_UMSK 0x0770 #define RADEON_SCRATCH_ADDR 0x0774 +#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x)) + #define GET_SCRATCH( x ) (dev_priv->writeback_works \ - ? readl( &dev_priv->scratch[(x)] ) \ + ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRAT CHOFF(x) ) \ : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) ) @@ -587,6 +582,7 @@ #define RADEON_TXFORMAT_ARGB4444 5 #define RADEON_TXFORMAT_ARGB8888 6 #define RADEON_TXFORMAT_RGBA8888 7 +#define RADEON_TXFORMAT_Y8 8 #define RADEON_TXFORMAT_VYUY422 10 #define RADEON_TXFORMAT_YVYU422 11 #define RADEON_TXFORMAT_DXT1 12 @@ -701,15 +697,10 @@ #define RADEON_RING_HIGH_MARK 128 - -#define RADEON_BASE(reg) ((unsigned long)(dev_priv->mmio->handle)) -#define RADEON_ADDR(reg) (RADEON_BASE( reg ) + reg) - -#define RADEON_READ(reg) readl( (volatile u32 *) RADEON_ADDR(reg) ) -#define RADEON_WRITE(reg,val) writel( (val), (volatile u32 *) RADEON_ADDR(reg )) - -#define RADEON_READ8(reg) readb( (volatile u8 *) RADEON_ADDR(reg) ) -#define RADEON_WRITE8(reg,val) writeb( (val), (volatile u8 *) RADEON_ADDR(reg) ) +#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) +#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) +#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) +#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) #define RADEON_WRITE_PLL( addr, val ) \ do { \ @@ -786,23 +777,12 @@ * Misc helper macros */ -#define LOCK_TEST_WITH_RETURN( dev ) \ -do { \ - if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || \ - dev->lock.pid != current->pid ) { \ - DRM_ERROR( "%s called without lock held\n", \ - __FUNCTION__ ); \ - return -EINVAL; \ - } \ -} while (0) - - /* Perfbox functionality only. */ #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ do { \ if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \ - u32 head = GET_RING_HEAD(&dev_priv->ring); \ + u32 head = GET_RING_HEAD( dev_priv ); \ if (head == dev_priv->ring.tail) \ dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \ } \ @@ -872,11 +852,11 @@ dev_priv->ring.tail = write; \ } while (0) -#define COMMIT_RING() do { \ +#define COMMIT_RING() do { \ /* Flush writes to ring */ \ - rmb(); \ - GET_RING_HEAD( &dev_priv->ring ); \ - RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \ + DRM_MEMORYBARRIER(); \ + GET_RING_HEAD( dev_priv ); \ + RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \ /* read from PCI bus to ensure correct posting */ \ RADEON_READ( RADEON_CP_RB_RPTR ); \ } while (0) @@ -902,17 +882,17 @@ \ if (write + _size > mask) { \ int i = (mask+1) - write; \ - if (__copy_from_user( (int *)(ring+write), \ + if (DRM_COPY_FROM_USER_UNCHECKED( (int *)(ring+write), \ _tab, i*4 )) \ - return -EFAULT; \ + return DRM_ERR(EFAULT); \ write = 0; \ _size -= i; \ _tab += i; \ } \ \ - if (_size && __copy_from_user( (int *)(ring+write), \ + if (_size && DRM_COPY_FROM_USER_UNCHECKED( (int *)(ring+write), \ _tab, _size*4 )) \ - return -EFAULT; \ + return DRM_ERR(EFAULT); \ \ write += _size; \ write &= mask; \ diff -Naur linux-2.4.36.2.orig/drivers/char/drm/radeon.h linux-2.4.36.2/drivers /char/drm/radeon.h --- linux-2.4.36.2.orig/drivers/char/drm/radeon.h 2008-05-21 03:25:34.000 000000 +0200 +++ linux-2.4.36.2/drivers/char/drm/radeon.h 2008-05-21 03:26:24.000000000 + 0200 @@ -51,7 +51,7 @@ #define DRIVER_DATE "20020828" #define DRIVER_MAJOR 1 -#define DRIVER_MINOR 7 +#define DRIVER_MINOR 8 #define DRIVER_PATCHLEVEL 0 /* Interface history: @@ -77,6 +77,9 @@ * and R200_PP_CUBIC_OFFSET_F1_[0..5]. * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian) + * 1.8 - Remove need to call cleanup ioctls on last client exit (keith) + * Add 'GET' queries for starting additional clients on different VT's. + * Add DRM_IOCTL_RADEON_CP_RESUME ioctl. */ #define DRIVER_IOCTLS \ [DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { radeon_cp_buffers, 1, 0 }, \ @@ -85,6 +88,7 @@ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_STOP)] = { radeon_cp_stop, 1, 1 }, \ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_RESET)] = { radeon_cp_reset, 1, 1 }, \ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_IDLE)] = { radeon_cp_idle, 1, 0 }, \ + [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_RESUME)] = { radeon_cp_resume, 1, 0 }, \ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_RESET)] = { radeon_engine_reset, 1, 0 }, \ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_FULLSCREEN)] = { radeon_fullscreen, 1, 0 }, \ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_SWAP)] = { radeon_cp_swap, 1, 0 }, \ @@ -105,11 +109,6 @@ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_IRQ_WAIT)] = { radeon_irq_wait, 1, 0 }, -#define USE_IRQS 1 -#if USE_IRQS -#define __HAVE_DMA_IRQ 1 -#define __HAVE_VBL_IRQ 1 -#define __HAVE_SHARED_IRQ 1 /* When a client dies: * - Check for and clean up flipped page state @@ -117,35 +116,34 @@ * * DRM infrastructure takes care of reclaiming dma buffers. */ -#define DRIVER_PRERELEASE() do { \ +#define DRIVER_PRERELEASE() \ +do { \ if ( dev->dev_private ) { \ drm_radeon_private_t *dev_priv = dev->dev_private; \ if ( dev_priv->page_flipping ) { \ radeon_do_cleanup_pageflip( dev ); \ } \ - radeon_mem_release( dev_priv->agp_heap ); \ + radeon_mem_release( filp, dev_priv->agp_heap ); \ + radeon_mem_release( filp, dev_priv->fb_heap ); \ } \ } while (0) -/* On unloading the module: - * - Free memory heap structure - * - Remove mappings made at startup and free dev_private. +/* When the last client dies, shut down the CP and free dev->dev_priv. */ -#define DRIVER_PRETAKEDOWN() do { \ - if ( dev->dev_private ) { \ - drm_radeon_private_t *dev_priv = dev->dev_private; \ - radeon_mem_takedown( &(dev_priv->agp_heap) ); \ - radeon_do_cleanup_cp( dev ); \ - } \ +/* #define __HAVE_RELEASE 1 */ +#define DRIVER_PRETAKEDOWN() \ +do { \ + radeon_do_release( dev ); \ } while (0) -#else -#define __HAVE_DMA_IRQ 0 -#endif + /* DMA customization: */ #define __HAVE_DMA 1 +#define __HAVE_DMA_IRQ 1 +#define __HAVE_VBL_IRQ 1 +#define __HAVE_SHARED_IRQ 1 /* Buffer customization: diff -Naur linux-2.4.36.2.orig/drivers/char/drm/radeon_irq.c linux-2.4.36.2/dri vers/char/drm/radeon_irq.c --- linux-2.4.36.2.orig/drivers/char/drm/radeon_irq.c 2008-05-21 03:25:34.000 000000 +0200 +++ linux-2.4.36.2/drivers/char/drm/radeon_irq.c 2008-05-21 03:26:24.000 000000 +0200 @@ -35,7 +35,6 @@ #include "drm.h" #include "radeon_drm.h" #include "radeon_drv.h" -#include "drm_os_linux.h" /* Interrupts - Used for device synchronization and flushing in the * following circumstances: @@ -55,34 +54,36 @@ * tied to dma at all, this is just a hangover from dri prehistory. */ -void DRM(dma_service)(int irq, void *arg, struct pt_regs *reg) +irqreturn_t DRM(dma_service)( DRM_IRQ_ARGS ) { drm_device_t *dev = (drm_device_t *) arg; drm_radeon_private_t *dev_priv = (drm_radeon_private_t *)dev->dev_private; u32 stat; - stat = RADEON_READ(RADEON_GEN_INT_STATUS) - & (RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT); + /* Only consider the bits we're interested in - others could be used + * outside the DRM + */ + stat = RADEON_READ(RADEON_GEN_INT_STATUS) + & (RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT); if (!stat) - return; + return IRQ_NONE; /* SW interrupt */ if (stat & RADEON_SW_INT_TEST) { - wake_up_interruptible( &dev_priv->swi_queue ); + DRM_WAKEUP( &dev_priv->swi_queue ); } /* VBLANK interrupt */ if (stat & RADEON_CRTC_VBLANK_STAT) { atomic_inc(&dev->vbl_received); - wake_up_interruptible(&dev->vbl_queue); - DRM(vbl_send_signals)(dev); + DRM_WAKEUP(&dev->vbl_queue); + DRM(vbl_send_signals)( dev ); } - /* Acknowledge all the bits in GEN_INT_STATUS -- seem to get - * more than we asked for... - */ + /* Acknowledge interrupts we handle */ RADEON_WRITE(RADEON_GEN_INT_STATUS, stat); + return IRQ_HANDLED; } static __inline__ void radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv) @@ -128,7 +129,7 @@ */ radeon_acknowledge_irqs( dev_priv ); - DRM_WAIT_ON( ret, dev_priv->swi_queue, 3 * HZ, + DRM_WAIT_ON( ret, dev_priv->swi_queue, 3 * DRM_HZ, RADEON_READ( RADEON_LAST_SWI_REG ) >= swi_nr ); return ret; @@ -149,7 +150,7 @@ if ( !dev_priv ) { DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ) ; - return -EINVAL; + return DRM_ERR(EINVAL); } radeon_acknowledge_irqs( dev_priv ); @@ -160,7 +161,7 @@ * by about a day rather than she wants to wait for years * using vertical blanks... */ - DRM_WAIT_ON( ret, dev->vbl_queue, 3*HZ, + DRM_WAIT_ON( ret, dev->vbl_queue, 3*DRM_HZ, ( ( ( cur_vblank = atomic_read(&dev->vbl_received ) ) - *sequence ) <= (1<<23) ) ); @@ -172,19 +173,18 @@ /* Needs the lock as it touches the ring. */ -int radeon_irq_emit(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long data) +int radeon_irq_emit( DRM_IOCTL_ARGS ) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_irq_emit_t emit; int result; - LOCK_TEST_WITH_RETURN( dev ); + LOCK_TEST_WITH_RETURN( dev, filp ); if ( !dev_priv ) { DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ) ; - return -EINVAL; + return DRM_ERR(EINVAL); } DRM_COPY_FROM_USER_IOCTL( emit, (drm_radeon_irq_emit_t *)data, @@ -192,9 +192,9 @@ result = radeon_emit_irq( dev ); - if ( copy_to_user( emit.irq_seq, &result, sizeof(int) ) ) { + if ( DRM_COPY_TO_USER( emit.irq_seq, &result, sizeof(int) ) ) { DRM_ERROR( "copy_to_user\n" ); - return -EFAULT; + return DRM_ERR(EFAULT); } return 0; @@ -203,16 +203,15 @@ /* Doesn't need the hardware lock. */ -int radeon_irq_wait(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long data) +int radeon_irq_wait( DRM_IOCTL_ARGS ) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_irq_wait_t irqwait; if ( !dev_priv ) { DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ) ; - return -EINVAL; + return DRM_ERR(EINVAL); } DRM_COPY_FROM_USER_IOCTL( irqwait, (drm_radeon_irq_wait_t *)data, @@ -240,7 +239,7 @@ (drm_radeon_private_t *)dev->dev_private; atomic_set(&dev_priv->swi_emitted, 0); - init_waitqueue_head( &dev_priv->swi_queue ); + DRM_INIT_WAITQUEUE( &dev_priv->swi_queue ); /* Turn on SW and VBL ints */ RADEON_WRITE( RADEON_GEN_INT_CNTL, @@ -251,8 +250,9 @@ void DRM(driver_irq_uninstall)( drm_device_t *dev ) { drm_radeon_private_t *dev_priv = (drm_radeon_private_t *)dev->dev_private; - if ( dev_priv ) { - /* Disable *all* interrupts */ - RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 ); - } + if (!dev_priv) + return; + + /* Disable *all* interrupts */ + RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 ); } diff -Naur linux-2.4.36.2.orig/drivers/char/drm/radeon_mem.c linux-2.4.36.2/dri vers/char/drm/radeon_mem.c --- linux-2.4.36.2.orig/drivers/char/drm/radeon_mem.c 2008-05-21 03:25:34.000 000000 +0200 +++ linux-2.4.36.2/drivers/char/drm/radeon_mem.c 2008-05-21 03:26:24.000 000000 +0200 @@ -34,23 +34,22 @@ #include "drm.h" #include "radeon_drm.h" #include "radeon_drv.h" -#include "drm_os_linux.h" /* Very simple allocator for agp memory, working on a static range * already mapped into each client's address space. */ static struct mem_block *split_block(struct mem_block *p, int start, int size, - int pid ) + DRMFILE filp ) { /* Maybe cut off the start of an existing block */ if (start > p->start) { - struct mem_block *newblock = kmalloc(sizeof(*newblock), GFP_KER NEL); + struct mem_block *newblock = DRM_MALLOC(sizeof(*newblock)); if (!newblock) goto out; newblock->start = start; newblock->size = p->size - (start - p->start); - newblock->pid = 0; + newblock->filp = 0; newblock->next = p->next; newblock->prev = p; p->next->prev = newblock; @@ -61,12 +60,12 @@ /* Maybe cut off the end of an existing block */ if (size < p->size) { - struct mem_block *newblock = kmalloc(sizeof(*newblock), GFP_KER NEL); + struct mem_block *newblock = DRM_MALLOC(sizeof(*newblock)); if (!newblock) goto out; newblock->start = start + size; newblock->size = p->size - size; - newblock->pid = 0; + newblock->filp = 0; newblock->next = p->next; newblock->prev = p; p->next->prev = newblock; @@ -76,20 +75,20 @@ out: /* Our block is in the middle */ - p->pid = pid; + p->filp = filp; return p; } static struct mem_block *alloc_block( struct mem_block *heap, int size, - int align2, int pid ) + int align2, DRMFILE filp ) { struct mem_block *p; int mask = (1 << align2)-1; for (p = heap->next ; p != heap ; p = p->next) { int start = (p->start + mask) & ~mask; - if (p->pid == 0 && start + size <= p->start + p->size) - return split_block( p, start, size, pid ); + if (p->filp == 0 && start + size <= p->start + p->size) + return split_block( p, start, size, filp ); } return NULL; @@ -109,92 +108,79 @@ static void free_block( struct mem_block *p ) { - p->pid = 0; + p->filp = 0; - /* Assumes a single contiguous range. Needs a special pid in + /* Assumes a single contiguous range. Needs a special filp in * 'heap' to stop it being subsumed. */ - if (p->next->pid == 0) { + if (p->next->filp == 0) { struct mem_block *q = p->next; p->size += q->size; p->next = q->next; p->next->prev = p; - kfree(q); + DRM_FREE(q, sizeof(*q)); } - if (p->prev->pid == 0) { + if (p->prev->filp == 0) { struct mem_block *q = p->prev; q->size += p->size; q->next = p->next; q->next->prev = q; - kfree(p); + DRM_FREE(p, sizeof(*q)); } } -#if 0 -static void print_heap( struct mem_block *heap ) -{ - struct mem_block *p; - - for (p = heap->next ; p != heap ; p = p->next) - DRM_DEBUG("0x%x..0x%x (0x%x) -- owner %d\n", - p->start, p->start + p->size, - p->size, p->pid); -} -#endif - /* Initialize. How to check for an uninitialized heap? */ static int init_heap(struct mem_block **heap, int start, int size) { - struct mem_block *blocks = kmalloc(sizeof(*blocks), GFP_KERNEL); + struct mem_block *blocks = DRM_MALLOC(sizeof(*blocks)); if (!blocks) return -ENOMEM; - *heap = kmalloc(sizeof(**heap), GFP_KERNEL); + *heap = DRM_MALLOC(sizeof(**heap)); if (!*heap) { - kfree( blocks ); + DRM_FREE( blocks, sizeof(*blocks) ); return -ENOMEM; } blocks->start = start; blocks->size = size; - blocks->pid = 0; + blocks->filp = 0; blocks->next = blocks->prev = *heap; memset( *heap, 0, sizeof(**heap) ); - (*heap)->pid = -1; + (*heap)->filp = (DRMFILE) -1; (*heap)->next = (*heap)->prev = blocks; return 0; } -/* Free all blocks associated with the releasing pid. +/* Free all blocks associated with the releasing file. */ -void radeon_mem_release( struct mem_block *heap ) +void radeon_mem_release( DRMFILE filp, struct mem_block *heap ) { - int pid = current->pid; struct mem_block *p; if (!heap || !heap->next) return; for (p = heap->next ; p != heap ; p = p->next) { - if (p->pid == pid) - p->pid = 0; + if (p->filp == filp) + p->filp = 0; } - /* Assumes a single contiguous range. Needs a special pid in + /* Assumes a single contiguous range. Needs a special filp in * 'heap' to stop it being subsumed. */ for (p = heap->next ; p != heap ; p = p->next) { - while (p->pid == 0 && p->next->pid == 0) { + while (p->filp == 0 && p->next->filp == 0) { struct mem_block *q = p->next; p->size += q->size; p->next = q->next; p->next->prev = p; - kfree(q); + DRM_FREE(q, sizeof(*q)); } } } @@ -211,10 +197,10 @@ for (p = (*heap)->next ; p != *heap ; ) { struct mem_block *q = p; p = p->next; - kfree(q); + DRM_FREE(q, sizeof(*q)); } - kfree( *heap ); + DRM_FREE( *heap, sizeof(**heap) ); *heap = 0; } @@ -235,17 +221,16 @@ } } -int radeon_mem_alloc(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long data ) +int radeon_mem_alloc( DRM_IOCTL_ARGS ) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; - drm_radeon_private_t *dev_priv = dev->dev_private; + DRM_DEVICE; + drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_mem_alloc_t alloc; struct mem_block *block, **heap; if ( !dev_priv ) { DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ) ; - return -EINVAL; + return DRM_ERR(EINVAL); } DRM_COPY_FROM_USER_IOCTL( alloc, (drm_radeon_mem_alloc_t *)data, @@ -253,7 +238,7 @@ heap = get_heap( dev_priv, alloc.region ); if (!heap || !*heap) - return -EFAULT; + return DRM_ERR(EFAULT); /* Make things easier on ourselves: all allocations at least * 4k aligned. @@ -262,15 +247,15 @@ alloc.alignment = 12; block = alloc_block( *heap, alloc.size, alloc.alignment, - current->pid ); + filp ); if (!block) - return -ENOMEM; + return DRM_ERR(ENOMEM); - if ( copy_to_user( alloc.region_offset, &block->start, + if ( DRM_COPY_TO_USER( alloc.region_offset, &block->start, sizeof(int) ) ) { DRM_ERROR( "copy_to_user\n" ); - return -EFAULT; + return DRM_ERR(EFAULT); } return 0; @@ -278,17 +263,16 @@ -int radeon_mem_free(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long data) +int radeon_mem_free( DRM_IOCTL_ARGS ) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_mem_free_t memfree; struct mem_block *block, **heap; if ( !dev_priv ) { DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ) ; - return -EINVAL; + return DRM_ERR(EINVAL); } DRM_COPY_FROM_USER_IOCTL( memfree, (drm_radeon_mem_free_t *)data, @@ -296,30 +280,29 @@ heap = get_heap( dev_priv, memfree.region ); if (!heap || !*heap) - return -EFAULT; + return DRM_ERR(EFAULT); block = find_block( *heap, memfree.region_offset ); if (!block) - return -EFAULT; + return DRM_ERR(EFAULT); - if (block->pid != current->pid) - return -EPERM; + if (block->filp != filp) + return DRM_ERR(EPERM); free_block( block ); return 0; } -int radeon_mem_init_heap(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long data) +int radeon_mem_init_heap( DRM_IOCTL_ARGS ) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_mem_init_heap_t initheap; struct mem_block **heap; if ( !dev_priv ) { DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ) ; - return -EINVAL; + return DRM_ERR(EINVAL); } DRM_COPY_FROM_USER_IOCTL( initheap, (drm_radeon_mem_init_heap_t *)data, @@ -327,11 +310,11 @@ heap = get_heap( dev_priv, initheap.region ); if (!heap) - return -EFAULT; + return DRM_ERR(EFAULT); if (*heap) { DRM_ERROR("heap already initialized?"); - return -EFAULT; + return DRM_ERR(EFAULT); } return init_heap( heap, initheap.start, initheap.size ); diff -Naur linux-2.4.36.2.orig/drivers/char/drm/radeon_state.c linux-2.4.36.2/d rivers/char/drm/radeon_state.c --- linux-2.4.36.2.orig/drivers/char/drm/radeon_state.c 2008-05-21 03:25:34.000 000000 +0200 +++ linux-2.4.36.2/drivers/char/drm/radeon_state.c 2008-05-21 03:26:24.000 000000 +0200 @@ -33,13 +33,13 @@ #include "drm_sarea.h" #include "radeon_drm.h" #include "radeon_drv.h" -#include "drm_os_linux.h" + /* ================================================================ * CP hardware state programming functions */ -static inline void radeon_emit_clip_rect( drm_radeon_private_t *dev_priv, +static __inline__ void radeon_emit_clip_rect( drm_radeon_private_t *dev_priv, drm_clip_rect_t *box ) { RING_LOCALS; @@ -913,7 +913,7 @@ do { /* Emit the next cliprect */ if ( i < nbox ) { - if (__copy_from_user( &box, &boxes[i], sizeof(box) )) + if (DRM_COPY_FROM_USER_UNCHECKED( &box, &boxes[i], size of(box) )) return; radeon_emit_clip_rect( dev_priv, &box ); @@ -1046,7 +1046,7 @@ do { if ( i < nbox ) { - if (__copy_from_user( &box, &boxes[i], sizeof(box) )) + if (DRM_COPY_FROM_USER_UNCHECKED( &box, &boxes[i], size of(box) )) return; radeon_emit_clip_rect( dev_priv, &box ); @@ -1063,7 +1063,8 @@ #define RADEON_MAX_TEXTURE_SIZE (RADEON_BUFFER_SIZE - 8 * sizeof(u32)) -static int radeon_cp_dispatch_texture( drm_device_t *dev, +static int radeon_cp_dispatch_texture( DRMFILE filp, + drm_device_t *dev, drm_radeon_texture_t *tex, drm_radeon_tex_image_t *image ) { @@ -1128,7 +1129,7 @@ break; default: DRM_ERROR( "invalid texture format %d\n", tex->format ); - return -EINVAL; + return DRM_ERR(EINVAL); } DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width ); @@ -1140,17 +1141,17 @@ /* Make a copy of some parameters in case we have to * update them for a multi-pass texture blit. - */ - height = image->height; - data = (const u8 *)image->data; - - size = height * blit_width; - - if ( size > RADEON_MAX_TEXTURE_SIZE ) { - height = RADEON_MAX_TEXTURE_SIZE / blit_width; + */ + height = image->height; + data = (const u8 *)image->data; + size = height * blit_width; - } else if ( size < 4 && size > 0 ) { - size = 4; + + if ( size > RADEON_MAX_TEXTURE_SIZE ) { + height = RADEON_MAX_TEXTURE_SIZE / blit_width; + size = height * blit_width; + } else if ( size < 4 && size > 0 ) { + size = 4; } else if ( size == 0 ) { return 0; } @@ -1162,63 +1163,64 @@ } if ( !buf ) { DRM_DEBUG("radeon_cp_dispatch_texture: EAGAIN\n"); - copy_to_user( tex->image, image, sizeof(*image) ); - return -EAGAIN; - } + DRM_COPY_TO_USER( tex->image, image, sizeof(*image) ); + return DRM_ERR(EAGAIN); + } - /* Dispatch the indirect buffer. - */ + /* Dispatch the indirect buffer. + */ buffer = (u32*)((char*)dev_priv->buffers->handle + buf->offset) ; dwords = size / 4; - buffer[0] = CP_PACKET3( RADEON_CNTL_HOSTDATA_BLT, dwords + 6 ); - buffer[1] = (RADEON_GMC_DST_PITCH_OFFSET_CNTL | - RADEON_GMC_BRUSH_NONE | - (format << 8) | - RADEON_GMC_SRC_DATATYPE_COLOR | - RADEON_ROP3_S | - RADEON_DP_SRC_SOURCE_HOST_DATA | - RADEON_GMC_CLR_CMP_CNTL_DIS | - RADEON_GMC_WR_MSK_DIS); - - buffer[2] = (tex->pitch << 22) | (tex->offset >> 10); - buffer[3] = 0xffffffff; - buffer[4] = 0xffffffff; - buffer[5] = (image->y << 16) | image->x; - buffer[6] = (height << 16) | image->width; - buffer[7] = dwords; - - buffer += 8; - - if ( tex_width >= 32 ) { - /* Texture image width is larger than the minimum, so we - * can upload it directly. - */ - if ( copy_from_user( buffer, data, dwords * sizeof(u32) ) ) { - DRM_ERROR( "EFAULT on data, %d dwords\n", dwords ); - return -EFAULT; - } - } else { - /* Texture image width is less than the minimum, so we - * need to pad out each image scanline to the minimum - * width. - */ - for ( i = 0 ; i < tex->height ; i++ ) { - if ( copy_from_user( buffer, data, tex_width ) ) { - DRM_ERROR( "EFAULT on pad, %d bytes\n", - tex_width ); - return -EFAULT; + buffer[0] = CP_PACKET3( RADEON_CNTL_HOSTDATA_BLT, dwords + 6 ); + buffer[1] = (RADEON_GMC_DST_PITCH_OFFSET_CNTL | + RADEON_GMC_BRUSH_NONE | + (format << 8) | + RADEON_GMC_SRC_DATATYPE_COLOR | + RADEON_ROP3_S | + RADEON_DP_SRC_SOURCE_HOST_DATA | + RADEON_GMC_CLR_CMP_CNTL_DIS | + RADEON_GMC_WR_MSK_DIS); + + buffer[2] = (tex->pitch << 22) | (tex->offset >> 10); + buffer[3] = 0xffffffff; + buffer[4] = 0xffffffff; + buffer[5] = (image->y << 16) | image->x; + buffer[6] = (height << 16) | image->width; + buffer[7] = dwords; + buffer += 8; + + if ( tex_width >= 32 ) { + /* Texture image width is larger than the minimum, so w e + * can upload it directly. + */ + if ( DRM_COPY_FROM_USER( buffer, data, + dwords * sizeof(u32) ) ) { + DRM_ERROR( "EFAULT on data, %d dwords\n", + dwords ); + return DRM_ERR(EFAULT); + } + } else { + /* Texture image width is less than the minimum, so we + * need to pad out each image scanline to the minimum + * width. + */ + for ( i = 0 ; i < tex->height ; i++ ) { + if ( DRM_COPY_FROM_USER( buffer, data, + tex_width ) ) { + DRM_ERROR( "EFAULT on pad, %d bytes\n", + tex_width ); + return DRM_ERR(EFAULT); + } + buffer += 8; + data += tex_width; } - buffer += 8; - data += tex_width; } - } - buf->pid = current->pid; - buf->used = (dwords + 8) * sizeof(u32); - - radeon_cp_dispatch_indirect( dev, buf, 0, buf->used ); - radeon_cp_discard_buffer( dev, buf ); + buf->pid = current->pid; + buf->used = (dwords + 8) * sizeof(u32); + radeon_cp_dispatch_indirect( dev, buf, 0, buf->used ); + radeon_cp_discard_buffer( dev, buf ); /* Update the input parameters for next time */ image->y += height; @@ -1263,31 +1265,28 @@ * IOCTL functions */ -int radeon_cp_clear( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int radeon_cp_clear( DRM_IOCTL_ARGS ) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_radeon_clear_t clear; drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS]; DRM_DEBUG( "\n" ); - LOCK_TEST_WITH_RETURN( dev ); + LOCK_TEST_WITH_RETURN( dev, filp ); - if ( copy_from_user( &clear, (drm_radeon_clear_t *)arg, - sizeof(clear) ) ) - return -EFAULT; + DRM_COPY_FROM_USER_IOCTL( clear, (drm_radeon_clear_t *)data, + sizeof(clear) ); RING_SPACE_TEST_WITH_RETURN( dev_priv ); if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS ) sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS; - if ( copy_from_user( &depth_boxes, clear.depth_boxes, + if ( DRM_COPY_FROM_USER( &depth_boxes, clear.depth_boxes, sarea_priv->nbox * sizeof(depth_boxes[0]) ) ) - return -EFAULT; + return DRM_ERR(EFAULT); radeon_cp_dispatch_clear( dev, &clear, depth_boxes ); @@ -1338,14 +1337,13 @@ /* Swapping and flipping are different operations, need different ioctls. * They can & should be intermixed to support multiple 3d windows. */ -int radeon_cp_flip(struct inode *inode, struct file *filp, unsigned int cmd, u nsigned long data ) +int radeon_cp_flip( DRM_IOCTL_ARGS ) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; DRM_DEBUG( "\n" ); - LOCK_TEST_WITH_RETURN( dev ); + LOCK_TEST_WITH_RETURN( dev, filp ); RING_SPACE_TEST_WITH_RETURN( dev_priv ); @@ -1358,16 +1356,14 @@ return 0; } -int radeon_cp_swap( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int radeon_cp_swap( DRM_IOCTL_ARGS ) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; DRM_DEBUG( "\n" ); - LOCK_TEST_WITH_RETURN( dev ); + LOCK_TEST_WITH_RETURN( dev, filp ); RING_SPACE_TEST_WITH_RETURN( dev_priv ); @@ -1381,11 +1377,9 @@ return 0; } -int radeon_cp_vertex( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int radeon_cp_vertex( DRM_IOCTL_ARGS ) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_device_dma_t *dma = dev->dma; @@ -1393,30 +1387,29 @@ drm_radeon_vertex_t vertex; drm_radeon_tcl_prim_t prim; - LOCK_TEST_WITH_RETURN( dev ); + LOCK_TEST_WITH_RETURN( dev, filp ); if ( !dev_priv ) { DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ) ; - return -EINVAL; + return DRM_ERR(EINVAL); } - if ( copy_from_user( &vertex, (drm_radeon_vertex_t *)arg, - sizeof(vertex) ) ) - return -EFAULT; + DRM_COPY_FROM_USER_IOCTL( vertex, (drm_radeon_vertex_t *)data, + sizeof(vertex) ); DRM_DEBUG( "pid=%d index=%d count=%d discard=%d\n", - current->pid, + DRM_CURRENTPID, vertex.idx, vertex.count, vertex.discard ); if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) { DRM_ERROR( "buffer index %d (of %d max)\n", vertex.idx, dma->buf_count - 1 ); - return -EINVAL; + return DRM_ERR(EINVAL); } if ( vertex.prim < 0 || vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) { DRM_ERROR( "buffer prim %d\n", vertex.prim ); - return -EINVAL; + return DRM_ERR(EINVAL); } RING_SPACE_TEST_WITH_RETURN( dev_priv ); @@ -1426,12 +1419,12 @@ if ( buf->pid != current->pid ) { DRM_ERROR( "process %d using buffer owned by %d\n", - current->pid, buf->pid ); - return -EINVAL; + DRM_CURRENTPID, buf->pid ); + return DRM_ERR(EINVAL); } if ( buf->pending ) { DRM_ERROR( "sending pending buffer %d\n", vertex.idx ); - return -EINVAL; + return DRM_ERR(EINVAL); } /* Build up a prim_t record: @@ -1470,11 +1463,9 @@ return 0; } -int radeon_cp_indices( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int radeon_cp_indices( DRM_IOCTL_ARGS ) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_device_dma_t *dma = dev->dma; @@ -1483,30 +1474,29 @@ drm_radeon_tcl_prim_t prim; int count; - LOCK_TEST_WITH_RETURN( dev ); + LOCK_TEST_WITH_RETURN( dev, filp ); if ( !dev_priv ) { DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ) ; - return -EINVAL; + return DRM_ERR(EINVAL); } - if ( copy_from_user( &elts, (drm_radeon_indices_t *)arg, - sizeof(elts) ) ) - return -EFAULT; + DRM_COPY_FROM_USER_IOCTL( elts, (drm_radeon_indices_t *)data, + sizeof(elts) ); - DRM_DEBUG( "%s: pid=%d index=%d start=%d end=%d discard=%d\n", - __FUNCTION__, current->pid, + DRM_DEBUG( "pid=%d index=%d start=%d end=%d discard=%d\n", + DRM_CURRENTPID, elts.idx, elts.start, elts.end, elts.discard ); if ( elts.idx < 0 || elts.idx >= dma->buf_count ) { DRM_ERROR( "buffer index %d (of %d max)\n", elts.idx, dma->buf_count - 1 ); - return -EINVAL; + return DRM_ERR(EINVAL); } if ( elts.prim < 0 || elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) { DRM_ERROR( "buffer prim %d\n", elts.prim ); - return -EINVAL; + return DRM_ERR(EINVAL); } RING_SPACE_TEST_WITH_RETURN( dev_priv ); @@ -1516,12 +1506,12 @@ if ( buf->pid != current->pid ) { DRM_ERROR( "process %d using buffer owned by %d\n", - current->pid, buf->pid ); - return -EINVAL; + DRM_CURRENTPID, buf->pid ); + return DRM_ERR(EINVAL); } if ( buf->pending ) { DRM_ERROR( "sending pending buffer %d\n", elts.idx ); - return -EINVAL; + return DRM_ERR(EINVAL); } count = (elts.end - elts.start) / sizeof(u16); @@ -1529,11 +1519,11 @@ if ( elts.start & 0x7 ) { DRM_ERROR( "misaligned buffer 0x%x\n", elts.start ); - return -EINVAL; + return DRM_ERR(EINVAL); } if ( elts.start < buf->used ) { DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used ); - return -EINVAL; + return DRM_ERR(EINVAL); } buf->used = elts.end; @@ -1571,57 +1561,51 @@ return 0; } -int radeon_cp_texture( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int radeon_cp_texture( DRM_IOCTL_ARGS ) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_texture_t tex; drm_radeon_tex_image_t image; int ret; - LOCK_TEST_WITH_RETURN( dev ); + LOCK_TEST_WITH_RETURN( dev, filp ); - if ( copy_from_user( &tex, (drm_radeon_texture_t *)arg, sizeof(tex) ) ) - return -EFAULT; + DRM_COPY_FROM_USER_IOCTL( tex, (drm_radeon_texture_t *)data, sizeof(tex ) ); if ( tex.image == NULL ) { DRM_ERROR( "null texture image!\n" ); - return -EINVAL; + return DRM_ERR(EINVAL); } - if ( copy_from_user( &image, + if ( DRM_COPY_FROM_USER( &image, (drm_radeon_tex_image_t *)tex.image, sizeof(image) ) ) - return -EFAULT; + return DRM_ERR(EFAULT); RING_SPACE_TEST_WITH_RETURN( dev_priv ); VB_AGE_TEST_WITH_RETURN( dev_priv ); - ret = radeon_cp_dispatch_texture( dev, &tex, &image ); + ret = radeon_cp_dispatch_texture( filp, dev, &tex, &image ); COMMIT_RING(); return ret; } -int radeon_cp_stipple( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int radeon_cp_stipple( DRM_IOCTL_ARGS ) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_stipple_t stipple; u32 mask[32]; - LOCK_TEST_WITH_RETURN( dev ); + LOCK_TEST_WITH_RETURN( dev, filp ); - if ( copy_from_user( &stipple, (drm_radeon_stipple_t *)arg, - sizeof(stipple) ) ) - return -EFAULT; + DRM_COPY_FROM_USER_IOCTL( stipple, (drm_radeon_stipple_t *)data, + sizeof(stipple) ); - if ( copy_from_user( &mask, stipple.mask, 32 * sizeof(u32) ) ) - return -EFAULT; + if ( DRM_COPY_FROM_USER( &mask, stipple.mask, 32 * sizeof(u32) ) ) + return DRM_ERR(EFAULT); RING_SPACE_TEST_WITH_RETURN( dev_priv ); @@ -1631,27 +1615,24 @@ return 0; } -int radeon_cp_indirect( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int radeon_cp_indirect( DRM_IOCTL_ARGS ) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_device_dma_t *dma = dev->dma; drm_buf_t *buf; drm_radeon_indirect_t indirect; RING_LOCALS; - LOCK_TEST_WITH_RETURN( dev ); + LOCK_TEST_WITH_RETURN( dev, filp ); if ( !dev_priv ) { DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ) ; - return -EINVAL; + return DRM_ERR(EINVAL); } - if ( copy_from_user( &indirect, (drm_radeon_indirect_t *)arg, - sizeof(indirect) ) ) - return -EFAULT; + DRM_COPY_FROM_USER_IOCTL( indirect, (drm_radeon_indirect_t *)data, + sizeof(indirect) ); DRM_DEBUG( "indirect: idx=%d s=%d e=%d d=%d\n", indirect.idx, indirect.start, @@ -1660,25 +1641,25 @@ if ( indirect.idx < 0 || indirect.idx >= dma->buf_count ) { DRM_ERROR( "buffer index %d (of %d max)\n", indirect.idx, dma->buf_count - 1 ); - return -EINVAL; + return DRM_ERR(EINVAL); } buf = dma->buflist[indirect.idx]; if ( buf->pid != current->pid ) { DRM_ERROR( "process %d using buffer owned by %d\n", - current->pid, buf->pid ); - return -EINVAL; + DRM_CURRENTPID, buf->pid ); + return DRM_ERR(EINVAL); } if ( buf->pending ) { DRM_ERROR( "sending pending buffer %d\n", indirect.idx ); - return -EINVAL; + return DRM_ERR(EINVAL); } if ( indirect.start < buf->used ) { DRM_ERROR( "reusing indirect: start=0x%x actual=0x%x\n", indirect.start, buf->used ); - return -EINVAL; + return DRM_ERR(EINVAL); } RING_SPACE_TEST_WITH_RETURN( dev_priv ); @@ -1709,10 +1690,9 @@ return 0; } -int radeon_cp_vertex2(struct inode *inode, struct file *filp, unsigned int cmd , unsigned long data ) +int radeon_cp_vertex2( DRM_IOCTL_ARGS ) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_device_dma_t *dma = dev->dma; @@ -1721,24 +1701,24 @@ int i; unsigned char laststate; - LOCK_TEST_WITH_RETURN( dev ); + LOCK_TEST_WITH_RETURN( dev, filp ); if ( !dev_priv ) { DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ) ; - return -EINVAL; + return DRM_ERR(EINVAL); } DRM_COPY_FROM_USER_IOCTL( vertex, (drm_radeon_vertex2_t *)data, sizeof(vertex) ); DRM_DEBUG( "pid=%d index=%d discard=%d\n", - current->pid, + DRM_CURRENTPID, vertex.idx, vertex.discard ); if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) { DRM_ERROR( "buffer index %d (of %d max)\n", vertex.idx, dma->buf_count - 1 ); - return -EINVAL; + return DRM_ERR(EINVAL); } RING_SPACE_TEST_WITH_RETURN( dev_priv ); @@ -1748,32 +1728,32 @@ if ( buf->pid != current->pid ) { DRM_ERROR( "process %d using buffer owned by %d\n", - current->pid, buf->pid ); - return -EINVAL; + DRM_CURRENTPID, buf->pid ); + return DRM_ERR(EINVAL); } if ( buf->pending ) { DRM_ERROR( "sending pending buffer %d\n", vertex.idx ); - return -EINVAL; + return DRM_ERR(EINVAL); } if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) - return -EINVAL; + return DRM_ERR(EINVAL); for (laststate = 0xff, i = 0 ; i < vertex.nr_prims ; i++) { drm_radeon_prim_t prim; drm_radeon_tcl_prim_t tclprim; - if ( copy_from_user( &prim, &vertex.prim[i], sizeof(prim) ) ) - return -EFAULT; + if ( DRM_COPY_FROM_USER( &prim, &vertex.prim[i], sizeof(prim) ) ) + return DRM_ERR(EFAULT); if ( prim.stateidx != laststate ) { drm_radeon_state_t state; - if ( copy_from_user( &state, + if ( DRM_COPY_FROM_USER( &state, &vertex.state[prim.stateidx], sizeof(state) ) ) - return -EFAULT; + return DRM_ERR(EFAULT); radeon_emit_state2( dev_priv, &state ); @@ -1825,13 +1805,13 @@ RING_LOCALS; if (id >= RADEON_MAX_STATE_PACKETS) - return -EINVAL; + return DRM_ERR(EINVAL); sz = packet[id].len; reg = packet[id].start; if (sz * sizeof(int) > cmdbuf->bufsz) - return -EINVAL; + return DRM_ERR(EINVAL); BEGIN_RING(sz+1); OUT_RING( CP_PACKET0( reg, (sz-1) ) ); @@ -1924,14 +1904,14 @@ DRM_DEBUG("\n"); - if (__get_user( tmp, &cmd[0])) - return -EFAULT; + if (DRM_GET_USER_UNCHECKED( tmp, &cmd[0])) + return DRM_ERR(EFAULT); cmdsz = 2 + ((tmp & RADEON_CP_PACKET_COUNT_MASK) >> 16); if ((tmp & 0xc0000000) != RADEON_CP_PACKET3 || cmdsz * 4 > cmdbuf->bufsz) - return -EINVAL; + return DRM_ERR(EINVAL); BEGIN_RING( cmdsz ); OUT_RING_USER_TABLE( cmd, cmdsz ); @@ -1957,22 +1937,22 @@ DRM_DEBUG("\n"); - if (__get_user( tmp, &cmd[0])) - return -EFAULT; + if (DRM_GET_USER_UNCHECKED( tmp, &cmd[0])) + return DRM_ERR(EFAULT); cmdsz = 2 + ((tmp & RADEON_CP_PACKET_COUNT_MASK) >> 16); if ((tmp & 0xc0000000) != RADEON_CP_PACKET3 || cmdsz * 4 > cmdbuf->bufsz) - return -EINVAL; + return DRM_ERR(EINVAL); if (!orig_nbox) goto out; do { if ( i < cmdbuf->nbox ) { - if (__copy_from_user( &box, &boxes[i], sizeof(box) )) - return -EFAULT; + if (DRM_COPY_FROM_USER_UNCHECKED( &box, &boxes[i], size of(box) )) + return DRM_ERR(EFAULT); /* FIXME The second and subsequent times round * this loop, send a WAIT_UNTIL_3D_IDLE before * calling emit_clip_rect(). This fixes a @@ -2031,16 +2011,15 @@ ADVANCE_RING(); break; default: - return -EINVAL; + return DRM_ERR(EINVAL); } return 0; } -int radeon_cp_cmdbuf(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long data ) +int radeon_cp_cmdbuf( DRM_IOCTL_ARGS ) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_device_dma_t *dma = dev->dma; drm_buf_t *buf = 0; @@ -2049,11 +2028,11 @@ drm_radeon_cmd_header_t header; int orig_nbox; - LOCK_TEST_WITH_RETURN( dev ); + LOCK_TEST_WITH_RETURN( dev, filp ); if ( !dev_priv ) { DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ) ; - return -EINVAL; + return DRM_ERR(EINVAL); } DRM_COPY_FROM_USER_IOCTL( cmdbuf, (drm_radeon_cmd_buffer_t *)data, @@ -2063,21 +2042,21 @@ VB_AGE_TEST_WITH_RETURN( dev_priv ); - if (verify_area( VERIFY_READ, cmdbuf.buf, cmdbuf.bufsz )) - return -EFAULT; + if (DRM_VERIFYAREA_READ( cmdbuf.buf, cmdbuf.bufsz )) + return DRM_ERR(EFAULT); if (cmdbuf.nbox && - verify_area( VERIFY_READ, cmdbuf.boxes, + DRM_VERIFYAREA_READ(cmdbuf.boxes, cmdbuf.nbox * sizeof(drm_clip_rect_t))) - return -EFAULT; + return DRM_ERR(EFAULT); orig_nbox = cmdbuf.nbox; while ( cmdbuf.bufsz >= sizeof(header) ) { - if (__get_user( header.i, (int *)cmdbuf.buf )) { + if (DRM_GET_USER_UNCHECKED( header.i, (int *)cmdbuf.buf )) { DRM_ERROR("__get_user %p\n", cmdbuf.buf); - return -EFAULT; + return DRM_ERR(EFAULT); } cmdbuf.buf += sizeof(header); @@ -2088,7 +2067,7 @@ DRM_DEBUG("RADEON_CMD_PACKET\n"); if (radeon_emit_packets( dev_priv, header, &cmdbuf )) { DRM_ERROR("radeon_emit_packets failed\n"); - return -EINVAL; + return DRM_ERR(EINVAL); } break; @@ -2096,7 +2075,7 @@ DRM_DEBUG("RADEON_CMD_SCALARS\n"); if (radeon_emit_scalars( dev_priv, header, &cmdbuf )) { DRM_ERROR("radeon_emit_scalars failed\n"); - return -EINVAL; + return DRM_ERR(EINVAL); } break; @@ -2104,7 +2083,7 @@ DRM_DEBUG("RADEON_CMD_VECTORS\n"); if (radeon_emit_vectors( dev_priv, header, &cmdbuf )) { DRM_ERROR("radeon_emit_vectors failed\n"); - return -EINVAL; + return DRM_ERR(EINVAL); } break; @@ -2114,13 +2093,15 @@ if ( idx < 0 || idx >= dma->buf_count ) { DRM_ERROR( "buffer index %d (of %d max)\n", idx, dma->buf_count - 1 ); - return -EINVAL; + return DRM_ERR(EINVAL); } buf = dma->buflist[idx]; if ( buf->pid != current->pid || buf->pending ) { - DRM_ERROR( "bad buffer\n" ); - return -EINVAL; + DRM_ERROR( "bad buffer %d %d %d\n", + buf->pid, current->pid, + buf->pending); + return DRM_ERR(EINVAL); } radeon_cp_discard_buffer( dev, buf ); @@ -2130,7 +2111,7 @@ DRM_DEBUG("RADEON_CMD_PACKET3\n"); if (radeon_emit_packet3( dev, &cmdbuf )) { DRM_ERROR("radeon_emit_packet3 failed\n"); - return -EINVAL; + return DRM_ERR(EINVAL); } break; @@ -2138,7 +2119,7 @@ DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n"); if (radeon_emit_packet3_cliprect( dev, &cmdbuf, orig_nb ox )) { DRM_ERROR("radeon_emit_packet3_clip failed\n"); - return -EINVAL; + return DRM_ERR(EINVAL); } break; @@ -2146,7 +2127,7 @@ DRM_DEBUG("RADEON_CMD_SCALARS2\n"); if (radeon_emit_scalars2( dev_priv, header, &cmdbuf )) { DRM_ERROR("radeon_emit_scalars2 failed\n"); - return -EINVAL; + return DRM_ERR(EINVAL); } break; @@ -2154,14 +2135,14 @@ DRM_DEBUG("RADEON_CMD_WAIT\n"); if (radeon_emit_wait( dev, header.wait.flags )) { DRM_ERROR("radeon_emit_wait failed\n"); - return -EINVAL; + return DRM_ERR(EINVAL); } break; default: DRM_ERROR("bad cmd_type %d at %p\n", header.header.cmd_type, cmdbuf.buf - sizeof(header)); - return -EINVAL; + return DRM_ERR(EINVAL); } } @@ -2173,23 +2154,22 @@ -int radeon_cp_getparam(struct inode *inode, struct file *filp, unsigned int cm d, unsigned long data) +int radeon_cp_getparam( DRM_IOCTL_ARGS ) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_getparam_t param; int value; if ( !dev_priv ) { DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ) ; - return -EINVAL; + return DRM_ERR(EINVAL); } DRM_COPY_FROM_USER_IOCTL( param, (drm_radeon_getparam_t *)data, sizeof(param) ); - DRM_DEBUG( "pid=%d\n", current->pid ); + DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID ); switch( param.param ) { case RADEON_PARAM_AGP_BUFFER_OFFSET: @@ -2212,13 +2192,26 @@ case RADEON_PARAM_AGP_BASE: value = dev_priv->agp_vm_start; break; + case RADEON_PARAM_REGISTER_HANDLE: + value = dev_priv->mmio_offset; + break; + case RADEON_PARAM_STATUS_HANDLE: + value = dev_priv->ring_rptr_offset; + break; + case RADEON_PARAM_SAREA_HANDLE: + /* The lock is the first dword in the sarea. */ + value = (int)dev->lock.hw_lock; + break; + case RADEON_PARAM_AGP_TEX_HANDLE: + value = dev_priv->agp_textures_offset; + break; default: - return -EINVAL; + return DRM_ERR(EINVAL); } - if ( copy_to_user( param.value, &value, sizeof(int) ) ) { + if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) { DRM_ERROR( "copy_to_user\n" ); - return -EFAULT; + return DRM_ERR(EFAULT); } return 0;